Wafer-level Characterization and Monitoring Platform for Single-Photon
Avalanche Diodes
Abstract
When developing a technology based on single-photon avalanche diodes
(SPADs), the SPAD characterization is mandatory to debug, optimize and
monitor the microfabrication process. This is especially true for the
development of SPAD arrays 3D integrated with CMOS readout electronics,
where SPAD testing is required to qualify the process, independently
from the final CMOS readout circuit. This work reports on a
characterization and monitoring platform dedicated to SPAD testing at
die and wafer level, in the context of a 3D SPAD technology development.
The platform relies on a dedicated integrated circuit made in a standard
CMOS technology and used in different configurations from a prototype
printed circuit board (die-level testing) to active probe cards
(wafer-level mapping). The platform gives full access to SPAD
characteristics in Geiger mode such as the dark noise, photon detection
efficiency and timing resolution. The integrated circuit and its
configuration are described in detail as well as results obtained on
different SPAD test structures. In particular, the dark count rate
mapping demonstrates the benefits of testing SPADs at wafer level at the
R&D stage.