Conclusion and Outlook

To perform cognitive and recognition workloads in the most efficient manner, hardware systems that implement neural network algorithms are required. A typical performance metric for computing systems, tera operation per second (TOPS), is extended to account for energy efficiency as TOPS per watt (TOPS/W). This study showed that nonvolatile resistive memories and selectors are attractive technologies that not only boost the TOPS/W in the systems up to a few tens of magnitude, which was a sufficient class to be used for recognition in real time but also ensure software-equivalent accuracy on various recognition tasks. Compared to digital SRAM as the binary synapse, the resistive memories stored analog information even in the small cell area. However, for accelerating the neural network computations on the entire neuromorphic system rather than single device, the multiple states of the analog resistive synaptic element needed to be tuned linearly by identical voltage pulses. Therefore, the aim of this review was to address recent progresses and strategies to solve the problem, considering the underlying working principle of each memory candidate. In summary, benchmarking and comparing key performance indicators was shown in Figure 6 to provide design options for building neuromorphic systems. Due to the commercialization of the PCM in the memory field, a solid understanding of physical mechanism and thorough reliability analysis that lead to the development of reliable devices with advanced compensation circuits can continue to expand the possibilities of the PCM for the neuromorphic computing systems. In addition to DNN, another spiking neural network for the next-generation neural network was implemented on PCM-based neuromorphic chips,[123] motivating and highlighting the need and importance of analog synaptic devices. However, the PCM seemed to be far from the ideal synaptic device due to the limited achievable conductance states and its nonlinear and asymmetric response to the consecutive identical pulses; hence the degradation of the recognition accuracy during the training. This is because the phase-change behavior is very sensitive to the compositions of the chalcogenide material. The composition of well-known GST materials was the result of optimizing the trade-off relationship between speed and operating current, making it difficult to modify the composition and materials to improve synaptic properties. Therefore, the studies have primarily attempted to subdivide the synaptic components such as arranging two PCM devices and adding 3T–1C devices to offset the shortcomings of unit PCM. The RRAM, which can operate at a lower operating current than the PCM and can be scaled at 10 nm, has been extensively studied for the synapses and has reasonably satisfied most requirements. In addition to achieving linear and symmetric weight update through innovative material and device engineering, defect-tolerant algorithms and circuitries have been developed to evaluate the reliability of each state and various failure modes. For memory applications, the range from 1 to 10 μA was the preferred operating current required for unit RRAM device considering the array size and sensing speed. Meanwhile, for neuromorphic VMM accelerators, most RRAM devices in the column may be required for simultaneous reading depending on the input vector in the worst case. Thus, the number of the RRAM devices placed in the column is related to the quantity of current that the external drive and sense circuits can handle, constraining the maximum allowable array size. In addition, it should be considered that a reduced current level of the RRAM distorted IV linearity induces an actual weighted sum current that is lower than expected, causing inference error. The most neuromorphic test-chips with peripheral circuits have been demonstrated with the PCM and RRAM synapses with 1T–1R configurations. The three-terminal transistor will eventually be replaced by the two-terminal selector depending on the applications. The area improvement is clear with the introduction of the selector, but conductance linearity as a function of voltage sweep and pulse for weighted sum and weight update, respectively, can be affected.[66] The increase in the operating voltage in the 1S–1R synapse due to the additional selector needs to be optimized while considering the operating power consumptions. The ECRAM that utilizes the ion transport across the entire area, not locally, is still in the early stages of research. The lateral conductance states can be maximally achieved because the ions provided vertically were sophistically controlled from the gate in the ECRAM. However, the dynamic range of the conductance extracted from minimum and maximum levels was low. Even at the expense of the occupied area loss, the nearly perfect synaptic behaviors of the ECRAM was attractive to be used as synaptic elements dedicated for on-chip training. The slow speed to drive the ions and uncertain reliability issues that can be affected by scaling need systematic further investigation through a deep understanding and linking of each role of the selected ions. The use of the ferroelectric polarization mechanism rather than ion-migration-enabled reliable conductance of the FeFET synapses to be controlled symmetrically and promptly. Nevertheless, the conductance related to the number of ferroelectric domains that are rotated in the device and updated by energy- and area-inefficient nonidentical pulse scheme. The variability, which is one of the noticeable reliability issues in the other resistive synaptic devices, is significantly low, but the retention and endurance of the multilevel conductance should be further verified. To date, the synaptic properties have been evaluated in the usual FeFET fabricated for memory applications. Specific engineering methodologies aimed at neuromorphic applications leave design spaces to allow for conductance update in the ferroelectric materials through the identical pulse. Device-level studies on the FeFET-based synapses have been improved in recent years, but it is noteworthy that simulation modeling that accurately describes the physical ferroelectric behavior and matches the experimental results is well-established.[124] Design exploration for kernel operation of convolutional neural networks and DNN accelerators based on simulated FeFET devices has been extensively studied to pioneer more diverse and appropriate options for using the FeFET synaptic elements.[125] For the MRAM with the highest maturity among the emerging memory technologies from manufacturing process and physics perspectives, the analogous behavior beyond reliable binary state has been observed by adopting a new writing mechanism called SOT. However, application flexibility is expected to be low because it is difficult to control the current range that can be obtained and the small on/off ratio (≈2×). Using different types of resistive memories and conventional devices in a hybrid configuration is considered the fastest way to implement fully functional neuromorphic systems compared with developing a single universal memory to perfectly satisfy all the tough criteria. This approach complemented the drawbacks of each memory with other devices, relaxing and alleviating requirements of synaptic devices. It also increases the degree of the freedom to use certain resistive memories that exhibit particularly prominent features such as excellent linearity of the conductance within a very short duration.