Transition to non von-Neumann architecture where the multiple synaptic array blocks for executing VMM in the place where the memories are stored in a similar manner are implemented, thereby eliminating memory wall bottleneck. Instead of binary synaptic weights based on SRAM, nonvolatile analog synaptic weights are preferred to maximize hardware performance in the view point of recognition accuracy and power efficiency. Single transistor structure or the resistive memory connected to either the transistor (1T–1R) or selector (1S–1R) configurations can be suitably used for the architecture, as shown in the bottom box. The portion of the neuronal elements also needs to be compact by exploring new devices and volatile memories, as shown in right box.