To date, several studies have attempted to improve the linear response of the conductance as a function of voltage and identical pulse train in the analog emerging memories for weighted sum and weight update operations, respectively. The absolutely small dynamic conductance step adversely becomes the most significant problem to have considerable effect on the accuracy of the hardware level beyond unit device improvement. Therefore, to compensate the imperfect synaptic devices, hybrid synaptic configuration has been proposed.
[103, 105] The purpose of the configuration is to subdivide the role in the training, thus relaxing stringent demands to be satisfied by a single synaptic device. Depending on the numerical importance in the neuromorphic systems, two pairs of conductance elements were newly configured to be a single synaptic element as follows
where
F defines a significant factor that indicates the numerical significance of the weight,
G+ and
G− denote the normal conductance values of the higher significant conductance (HSC) pair, and
g+ and
g− represent newly introduced conductance values of the lower significance conductance (LSC) pair. It has been recently discovered that the use of capacitors can result in significantly linear conductance update.
[104] More specifically, the capacitor based synaptic configuration comprised three parts: 1) a readout FET connected to the capacitor, 2) a p-type FET (pFET), and 3) an n-type FET (nFET) for adding and subtracting charge to the capacitor, indicated in 3T–1C configuration. The charge on the capacitor represented the synaptic weight, and it was elaborately varied by the gate voltage for charging and discharging to the capacitor node. However, intrinsic volatile properties of the capacitor, which take natural decay of the charge, should be refreshed periodically. Through exploiting the benefit of the linearly updated synaptic weight even for a short duration, the volatile component was defined to be LSC (
g+ and
g−). In other words, during training, only the LSC pair was updated linearly and bidirectionally. The trained weights were thereafter transferred to the nonvolatile PCM devices serving as HSC (
G+ and
G−), so that the weights could be stored for a long time. Consequently, the 3T–1C and 2 PCMs represented the weight. This approach enabled software-comparable hardware performance with accuracy of ≈98% and 88% for the MNIST and Canadian Institute for Advanced Research (CIFAR)-10, respectively.
As an extended concept, the role of the volatile capacitor component was replaced by a nonvolatile FeFET device, thereby saving the area and power substantially.
[106] The pFET and nFET were used for a similar purpose of providing and distracting charges, but the degree of the charge accumulation proportional to the gate automatically affected the polarization in the FeFET. Gate voltage was applied to update the weight induced through the polarization; thus, the update was automatically encoded at the FeFET. This simplified process in the two-source transistors and one-FeFET (2T–1F) can eliminate leakage concern due to the nonvolatility and minimal device area occupied by the capacitors and 2 PCMs. These hybrid synapses were expected to exhibit better training accuracy at the expense of the area.