The proposed comparator alongside main waveforms is illustrated in
Figure 1. In the first stage, pre-amplifier, includes input transistors\(M_{1-4}\), and two tail transistors. The other transistors are
included in the dynamic latch structure. \(M_{13}\) and \(M_{14}\) set
up a positive feedback so-called ”Thyristor” which has been used in some
circuits [9]. As shown in Figure 1. b,
during the reset phase, nodes \(O_{1+\ }\)and\(\ O_{1-}\) are
discharged to the ground and nodes \(O_{2+\ }\)and \(O_{2-}\) are
charged to \(\text{Vdd}\ \)by relative transistors. In other words,
thyristors are off. Supposing \(I_{n+}>I_{n-}\), as the evaluation
phase starts node \(O_{1+\ }\)is charged much faster than\(O_{1-\ }\)by input transistors \(M_{1-2}\). Likewise, node\(O_{2+\ }\)is discharged faster than \(O_{2-\ }\) by input
transistors \(M_{3-4}\). It is only needed node \(O_{1+\ }\)is
charged to \(v_{\text{tn}}\) or \(O_{2+\ }\)discharged to\({Vdd-v}_{\text{tp}}\) where \(v_{\text{tn}}\ \)and \(v_{\text{tp}}\)are the threshold voltages of PMOS and NMOS transistors. Then, in due
time, the thyristor is activated and promptly flips its state. In this
scenario, the left thyristor (\(M_{13}\) and \(M_{14}\)) of the
comparator
is
activated sooner than the right one (\(M_{15}\) and \(M_{16}\)). So,\(M_{9}\) is turning on sooner than \(M_{10}\) and dynamic latch
provides the final outputs (Out+ and Out-). At low common-mode input
voltages, PMOS input transistors (\(M_{1},\ M_{2}\)) are accountable to
activate thyristors and NMOS input transistors (\(M_{3},\ M_{4}\)) are
obligated to do the same task at the high common-mode input voltages.
Results: The proposed
comparator is designed in a standard 180nm CMOS technology with load
capacitance of 2.5 fF implemented by MOM cap (which are not shown), with
the operating frequency of \(1MHz\) and \(Vdd=0.6V\). The layout of
the circuit is shown in Figure 2. Transistors are designed with large
sizes to attain low offset voltage which results in 37µm ×44 µm area
occupation.