A 0.6V rail-to-rail regenerative
comparator with a thyristor-based latch
Hadi Pahlavanzadeh, Mohammad Azim Karami ̵⃰
School of electrical engineering, University of Science and
Technology of Iran, Hengam St., Resalat Square, Tehran , 1684613114,
Iran.
Email: Karami@iust.ac.ir
A
low voltage two-stage rail-to-rail regenerative comparator is presented.
For the first time, a thyristor-based latch is introduced in this work,
enabling the comparator’s rail-to-rail operation. The proposed
comparator is post-layout simulated in a standard 180nm CMOS technology.
The results certify that the comparator’s delay and power are less than
28ns and 230nW with 0.6V supply voltage and 1MHz sample rate. The total
input-referred offset voltage (3std+mean) is less than 6.2mV over the
entire rial-to-rail common-mode voltage range. In comparison with
similar works the proposed comparator has the lowest delay and offset
and achieves the best FOM.
Introduction:For many energy-limited applications like energy harvesting systems,
battery-operated systems, and implantable biomedical devices, operating
in low-supply voltage is paramount. Comparators are the ubiquitous block
of such applications mixed-signal circuit design
[1, 2].
However, designing a
high-performance comparator with low-supply voltage operation is very
challenging. First, low supply voltage operation restricts comparator’s
common-mode input range, important for some ADCs like successive
approximation register (SAR) and Flash ADC
[3]. Next, once the supply voltage
decreased, transistors operate mainly in the subthreshold region where
transistors’ threshold voltage offset contribution to total offset
increases. Hence, a large transistor size is required, resulting in
higher power and area consumption [4].
This is while the transistors’
threshold voltage scaling could not succeed at the same rate of supply
voltage in modern CMOS technologies, attaining a low comparison time is
difficult[5].Circuit Design: Using bulk-driven transistor is the most popular
technique when it comes to designing a low-supply voltage-operated
comparator. A single-stage regenerative comparator is designed in
[6] with this technique which has a
limited input common-mode range. This limitation is resolved by the
non-clocked bulk-driven comparator, implemented in
[7].
Generally, this technique
increases leakage currents and decreases the comparator’s power
efficiency. A rail-to-rail synthesizable comparator is pioneered in
[8] which achieves low power
consumption but a very long comparison time. In this work without
complicating the design, a novel energy-efficient rail-to-rail two-stage
high-speed and low offset regenerative comparator is presented.