Table 2: Comparison table.
a: simulation b: measurement FOM= (power × offset)/fop
comparator design, in order to genuinely compare the performance of the comparators, the FOM introduced in [5] is utilized which the energy of comparison multiplied by offset voltage. As can be seen, the proposed comparator achieves the best FOM in comparison with similar works.
Conclusion: An energy efficient two-stage regenerative comparator is presented. The second stage utilizes thyristor-based dynamic latch with enable rail-to-rail operation of the comparator. The presented comparator is realized in circuit level using a 180nm standard CMOS technology. The post-layout simulation results corroborate that power and delay of the comparator is no more than 230nW and 28nW with 0.6V supply voltage and 1MHz clock frequency. The total offset of the comparator within rail-to-rail common-mode range, is less than 6.2mV. Considering the overall performance, the proposed comparator attained the best FOM in comparison with other state-of-the-art works. The proposed comparator is well suited to be utilized in energy harvesting systems and low voltage ADCs.