In this study, we investigated a new structure of a protective meander line (ML): a meander microstrip line (MSL) with two passive conductors. The existing theory of ultra-short pulse (USP) attenuation in MLs is presented for the first time. Based on this theory, we determined the number of decomposed pulses at the output of the MSL line with two passive conductors, and, for the first time, formulated the conditions for pulse decomposition in the line. The folding of the MSL line into non-core turns was studied in detail. As a result of this study, we proposed a new theory that involves the utilization of additional groups of decomposed pulses for enhanced USP attenuation. These additional groups were thoroughly examined, and the delays of pulses from these groups were defined. This analysis allowed identifying the reason for their appearance. It was revealed that folding the meander line into non-core turns allows further attenuation of the USP amplitude, which increases with the increase of the number of non-core turns. To validate the obtained simulation results, we performed experimental measurements and obtained good consistency of the results. The N-norms analysis demonstrated that combined use of such folding and passive conductors reduces the probability of electrical breakdown, arc discharge, and dielectric breakdown. The maximum USP attenuation at the output was 24.9 dB. As a result of useful signal integrity analysis, it is proposed to use a folded meander microstrip line (MSL) together with a USB 2.0 “Full-speed” interface with a data transfer rate of 12 Mbit/s. In addition, it is proposed to use such MSLs in DC power circuits.

Multi module isolated converters (MMICs) find extensive application in various DC-DC applications due to their remarkable features of galvanic isolation, bi-directional power flow, high power density and enhanced efficiency. However, voltage and current sharing among the converter modules are the most significant issues in MMICs. This paper proposes Multi-port Integrated-Magnetics Transformers (MpIMTs) which address the input-output DC-link voltage imbalances within an ISOS converter. The proposed transformers ensure the input voltage sharing (IVS) and output voltage sharing (OVS) through balancing windings within their structures, thus substitutes the complicated active control scheme with the balancing winding. Besides, the input side and output side modules are decoupled from each other, thus the impact of parameters variation and inter-module energy transfer during a transient of one side does not reflect to the other side. These properties are achieved by proposing a custom-designed core and an off the shelf available U core assembled MpIMTs. The magnetic and electrical equivalent along with the design criteria of the balancing winding are also presented. Furthermore, the paper includes the comparative analysis of the proposed transformers which reveals that while the U-core MpIMT offers simplified construction, it comes at the expense of slightly reduced efficiency compared to the custom-designed MpIMT. Finally, the proposed U core MpIMT is validated through a laboratory prototype.

The detection of high voltage permanent magnet motors has always been a big problem due to the interference of high voltage and magnetic field on the diagnosis. Especially the magenetic tile of the motor, the failure of the magenetic tile will directly lead to the operation failure of the motor. We propose Multi-view Unsupervised Consistent Soft-label Feature Selection(MUCSFS). This method constructed consistent pseudo-labels through soft labels of clustering affinity of each view sample and constructed the model by integrating selection constraints into the mapping model. This model is used to filter the fault data set to get the feature subset, and the feature subset is used to cluster. We verify the effectiveness of the method by simulating multi-view data and through the fault clustering experiment of the magnetic tile fault data set of high voltage motor, it is confirmed that our method can effectively cluster the fault categories.

The present study is devoted to articulating a modified Folded-Cascode circuit, to make Folded-Cascode structures an attractive configuration as a Transimpedance Amplifier (TIA) for being employed in Giga-bit per second optical communication receiver systems. Giga-bps communication receivers are highly necessitating circuits to isolate the input parasitic capacitance of the photodiode. The present modification makes Folded Cascodes comparable to the famous Regulated Cascode (RGC) structures by isolating this parasitic capacitor almost by the same quantity. The system is shown to be capable of operating at 2.5Gbps up to 8Gbps data rate with a fixed bandwidth. The paper analyzes and evaluates the designed circuit mathematically, and the obtained simulated results from Cadence using TSMC 65nm CMOS validate the suitability of the modified circuit as a transimpedance amplifier.

This paper presents a compact CMOS tunable positive and negative active inductor simulator (AIs), positive capacitance and resistance multiplier and negative capacitance and resistance simulator. The proposed design use only one analog building block (ABB) and three passive elements. Applications in the design of different types of tunable filters and parasitic compensation are also presented. The functionality of the design is confirmed using Tanner Tspice in 0.18µm TSMC CMOS technology. Simulation results indicate that the proposed design is superior to previous arts in many aspects.

By multiplying with the continuous factor (CF), the conventional Class- F / F - 1 , Class-J power amplifier (PA) can be expanded to their corresponding continuous modes, resulting in a great degree of freedom for broadband design. However, this method can hardly apply to other types of PAs. In view of this problem, the continuous mode is deeply analyzed from the perspective of equation solving for the first time, and a general theory for high-efficiency broadband continuous PA design is proposed. In this theory, the continuous impedance space does not rely on a mapping relationship achieved by multiplying with the CF, but on a direct solution of the high-efficiency equations to obtain the broadband design space. This approach is simpler and has the potential to provide greater design space. As a validation, this theory is used for the analysis of Class-E PAs and a new continuous Class-E (NC-E) PA is presented. With knee-point voltage and finite harmonics taken into account, this type of PA greatly expands the broadband design space of Class-E PAs, and also has the advantage of harmonic matching. The NC-E PA is designed and manufactured using GaN HEMT CGH40010F, which achieves 40.6∼41.6dBm output power and 66.2%∼74.2% drain efficiency (DE) in the frequency band of 2.5-3.8GHz.

Variable supply voltage-clustered voltage scaling (VS-CVS) is an effective way to decrease power consumption without compromising performance. One of the major challenges in VS-CVS design is that level converting flip-flops(LCFFs) not only need to have low power consumption but also high performance. In this paper, we propose two new structures of LCFF: the data branch sharing LCFF based on conditional charging (DBS-LCFFCC) and the data branch sharing LCFF based on precharging (DBS-LCFFP).The new structures adopt a data branch sharing scheme to improve the speed of the circuit as well as to reduce the number of transistors. Based on simulation results using HSPICE with PTM 32nm CMOS technology, the proposed LCFFs show an improvement of 19.2% to 67.2% and 41.6% to 76.3% in power-delay-product (PDP) at 50% data switching activity, respectively, compared to other advanced LCFFs.

In this paper, for standalone and grid-connected PV systems, a three-phase simplified split-source inverter (SSI) is proposed and controlled using a model-predictive control (MPC). The maximum power point tracking (MPPT) approach used is an incremental conductance method based on a PI controller for both systems. The standalone system is composed of PV modules, a three-phase SSI, and a bidirectional power DC-DC converter that connects a battery bank and a DC-side capacitor. The output AC voltages of SSI are controlled using model-predictive control. The bidirectional power DC/DC converter regulates the DC-link voltage (DCLV). The grid-connected system consists of PV modules, a three-phase SSI, and an AC-side L-filter. The DC-link PI controller generates reference currents for the MPC algorithm. The MPC uses these reference currents to adjust and deliver the PV power to the grid while regulating the DCLV. The PI controllers’ parameters are selected for both systems using the Harris Hawks optimization method. Both PV systems simulation results show that under various operating conditions, they have succeeded in fixing a DCLV and producing a high-quality AC output voltage and current at low THD. Experimental results for the three-phase standalone PV system used to verify the system’s performance.

Summary: This paper proposes a 1/f noise optimized correlated multiple sampling (NOCMS) technique based on differentiated sampling weights for CMOS image sensor. Transfer functions of standard CMS and NOCMS for analyzing the suppression effect of random noise respectively are derived based on the Fourier Transform theory. NOCMS shows a dramatic advantage in the suppression of 1/f noise. For implementing NOCMS, the ramp generator provides multiple sets of ramps with different slopes to quantize the reset and signal voltages. Sampling weights are increased with the decrease of ramp slopes. The last reset and first signal values are weighted more due to their potentially higher correlations. Simulation results under 110nm CMOS technology illustrate that the ADC achieves DNL of −0.80/+0.70LSB and INL of −0.70/+0.90LSB after the NOCMS operation. The input-referred random noise is 142.9µV rms under standard CMS and 120.9µV rms under NOCMS when the number of samples equals 8. The noise reduction effect is improved by 15%. NOCMS makes it possible to further reduce 1/f noise of CMOS image sensor.

Bipolar junction transistors (BJTs) are widely used in various electronic systems, and the establishment of the electromagnetic compatibility (EMC) model for BJTs is crucial for EMC analysis of these systems, such as high-frequency circuits. In this paper, a BJT EMC model that satisfies both functionality and EMC analysis requirements was established based on physical characteristic measurement. Firstly, comprehensive and systematic methods for measurement and extracting SPICE parameters based on physical BJTs are presented, including a proposed curve-fitting calculation method for extracting barrier capacitance parameters. Secondly, an analysis of the impact of major BJT electrical characteristics parameters was conducted, leading to the identification of important model parameters affecting BJT functionality and EMC. Finally, the primary BJT model was optimized using the simplex method, and a method for EMC analysis and verification of the BJT model was presented. The experimental and simulation results are in good agreement, and the established model meets the accuracy requirements for both EMC and functionality. Therefore, the proposed method is feasible and suitable for the EMC modeling of BJTs.

Systems with non-Hermitian Hamiltonians, especially those exhibiting parity-time ( PT ) symmetry, are of particular interest as they can describe physical open systems with balanced loss into and gain from the environment. In this context, the study of eigenvalue locations and the corresponding phase transitions as a function of the degree of non-Hermiticity γ is accomplished hereby using feedback theory. This approach provides insight about the behavior of these systems and allows generalization of the results for higher-order ones. The proposed ideas are analyzed in detail for a class of coupled resonant circuit chains.

In this paper, a noteworthy compact dual band wireless power transfer (DB-WPT) system is presented and studied. This system is proposed using interdigital capacitor which reduced the size of the whole system and accomplished high efficiencies. An interdigital capacitor is printed in the ground plane of the design and loaded with a chip capacitor to produce dual bands. The operation of the system is verified by fabricating the proposed DB-WPT system, which shows measured coupling efficiencies of 96 % and 98.8 % at 0.53 and 1.1 GHz, respectively at a transfer space of 12 mm. The fabricated structure has dimensions of 13.5 mm × 20 mm. The results show good agreement between the circuit model and the measurements. The idea of this design makes it applicable for compact near field WPT applications.

A novel transformerless three-phase unidirectional bridgeless flying capacitor (UBFC) rectifier for medium-voltage and high-voltage applications is presented by this paper. The rectifier consists of three single-phase rectifiers in wye connection, the DC outputs of the three single-phase rectifiers are connected in parallel to provide a high common DC-link bus which makes it convenient to connect with NPC or FC multilevel inverters. To avoid phase to phase current circulation, an additional inductor and diode are added to each single-phase rectifier. Compared with conventional bidirectional multilevel converters, only half IGBTs are employed with lower voltage stress, line-frequency transformers are no longer be required, which makes the proposed rectifier has a series of advantages such as reduced cost, simplified control complexity, increased reliability and improved overall efficiency. The basic operating principle of the proposed rectifier in continuous conduction mode is discussed, an improved carrier-based level-shifted PWM modulation method integrated with voltage balancing and the double closed-loop control strategy are proposed to achieve more voltage levels and keep the flying capacitors in balance. The feasibility of proposed rectifier is verified by the simulation as well as experimental results.

A coupled inductor based on dual switches buck-boost converter is proposed in the article, which can be used in renewable energy applications. Wide conversion ratio can be realized by regulating turns ratio of the coupled inductor and the duty cycle. The topology has a quadratic- like voltage gain, and the low voltage stress and current stress. Combing the passive clamping circuit to recover leakage energy, the voltage spikes of power switches are suppressed, improving the efficiency. Moreover, it has the merits of continuous input current and common ground. To demonstrate the superior performances of the presented converter, the principle of operation and steady-state analysis are presented in detail. At last, a 100 W experimental prototype was designed to verify the correctness of the theoretical analysis, with a maximum efficiency of 95.7% in step-up mode and 96.8 % in step-down mode.

This paper presents a low dropout regulator (LDO) with a wide input voltage range and high power supply rejection (PSR) for Hall sensor front-end circuits, which is fabricated with a 0.18 𝜇m BCD process. A topology in which a closed-loop charge pump biases the gate of two-stage cascode NMOS pass transistors is proposed to increase immunity to Electro-Magnetic Interference (EMI) capability for automotive applications. Furthermore, a power-down protection circuit is proposed to maintain the reliability of the system, and a novel implementation of the charge pump unit is presented to improve the influence of the body effect. Detailed derivation regarding the analyses of the simplified small-signal model of the closed-loop charge pump, the loop stability, and the PSR at various frequency bands is given. Simulation and measurement results show that the proposed LDO can operate with the input voltage from 5 V to 40 V, providing up to 60 mA current drive capability, and its minimum operating voltage is 2.5 V with a 10 mA load capacity. Moreover, results verify that measured PSR is better than -45 dB at 1.5 kHz, and measured PSR is better than - 30 dB at 15 MHz. The results confirm that the obtained parameters of line and load regulations are significantly improved to 1.86 mV/V and 1.75 mV/mA, respectively.

In this article, we propose a fast 3D-IC floorplanning method for hard macro-blocks that includes a thermal management scheme. It applies a genetic algorithm constituted by an optimal combination of crossover and mutation operations to identify the optimal solution for design variables, namely, total wire length, number of through-silicon vias (TSVs), and maximum average layer power density. The proposed method additionally makes use of a unique TSV placement scheme that arranges TSVs next to their respective functional blocks. To enable efficient heat transmission to the ambient environment, layers with higher power densities are placed closer to the heat sink. The proposed 3D-IC floorplanning approach provides the fewest TSVs, the lowest peak temperature, and promising values of wire length within the least amount of computation time. Compared to the recent fast thermal analysis for fixed-outline 3D-floorplanning, it generates 13.14% shorter wire length, 39.27% lower peak temperature, and 34.35% lesser number of TSVs on average with significant improvement in computation time, while analyzing GSRC thermal benchmark circuits.

It is well-known that DC-DC boost converters are cascaded with DC-AC inverters for grid connection of the photovoltaic (PV) systems. In the traditional control approaches, the mentioned DC-DC and DC-AC converters are controlled separately to facilitate the controller design problem. However, from the controller design viewpoint, the overall structure of the grid connected PV generator is a multi-input multi-output (MIMO) system. The duty-cycle of the DC-DC converter and Inverter modulation index are the control inputs and on the other hand, generated photovoltaic DC power, and exported power to the grid are control outputs. Moreover, the inverter DC link voltage should be stabilized by the closed-loop controller as well as an internal control output. If controllers are designed separately, it means that the interaction between DC-DC and DC-AC controllers isn’t considered accurately and since the isolated models of DC-DC converter and DC-AC inverter are extracted based on some approximated assumptions, separate controller design cannot guarantee stability and robustness of the whole system in a wide range of operation. To cope with these problems, in this paper, a novel MIMO sliding mode controller (SMC) is developed for comprehensive closed-loop control of the DC-DC boost converter cascaded with a single-phase DC-AC grid connected photovoltaic inverter. In the proposed approach, the dynamic model of whole system is developed comprehensively at first and then a unique MIMO controller is designed to control both DC-to-AC and DC-to-DC converters together. To cope with the nonlinear characteristic of the system and uncertainty of model parameters in a wide range, a fixed-frequency SMC is developed using the comprehensive state space model of the closed loop system. In the proposed MIMO-SMC controller, the AC power (which is exported to the grid) and operating point of the PV source are controlled via inverter modulation index and duty cycle of the DC-DC boost converter respectively. Another major advantage of the proposed system is mitigating the non-minimum phase characteristic of the boost converter through the indirect control of inverter DC link capacitor. To evaluate the performance of the designed control system, simulation results are compared with a standard linear PI controller. It is shown that the developed system has zero steady-state error and enjoys faster dynamic response during the start-up and step changes of AC and DC current references. Moreover, it can maintain the stability of closed-loop systems in a wide range of operations.

By integrating the Four Switch Buck-Boost (FSBB) PFC and full-bridge LLC resonant converter, a novel single-stage FSBB-LLC AC-DC converter is proposed. Moreover, a dual-loop feedback control strategy based on PFM/PWM hybrid modulation is proposed for obtaining the desired bus voltage and stable output voltage. The bus voltage feedback loop is utilized to regulate the bus voltage by selecting the boost or buck-boost mode; the output voltage feedback loop is employed to stabilize the output voltage by adjusting the switching frequency or phase shifting angle. Furthermore, an optimal parameter design based on power balance principle is also derived. The experimental results of an 85~300V input, 12V/25A output prototype demonstrate that: (1) low and narrow bus voltage of 240~340V is achieved under the entire input and output condition; (2) the LLC cell operates as a DCX converter over the whole load range as the input voltage exceeds 120V; (3) the output voltage is well regulated even under the no-load condition; (4) ZVS feature for the shared main switches is still maintained; (5) a peak efficiency of 90.9% and PF values above 0.987 are achieved.