Despite the use of High-k gate stacks, poor channel electrostatics at short channel lengths has limited the applicability of conventional Bulk MOSFETs. With the use of Ferroelectric materials in the gate stack, enhanced transverse (gate) electric field has the potential to enable greater scalability, which needs to be further explored in the context of planar Bulk MOSFETs. In this paper, we firstly present the design of an optimized N-channel Partially Junction-less Bulk MOSFET with a view to suppressing various leakage mechanisms, while also taking channel quantization effects into account. Through detailed process simulations, the process steps required to achieve this device design are determined, thus providing a more practical appraisal of the feasibility of the device. We then identify the thickness of the Ferroelectric layer over the existing gate stack with a view to achieve steep sub-threshold slope (SS) while simultaneously ensuring hysteresis-free characteristics, including enhanced Analog as well as Digital performance of the device.

Ultra-thin body (UTB) devices are being used in many electronic applications operating over a wide range of temperatures. The electrostatics of these devices depends on the band structure of the channel material, which varies with temperature as well as channel thickness. The semi-empirical tight binding (TB) approach is widely used for calculating channel thickness dependent band structure of any material, at a particular temperature, where TB parameters are defined. For elementary semiconductors like Si, Ge and compound semiconductors like GaAs, these TB parameters are generally defined at only 0 K and 300 K. This limits the ability of the TB approach to simulate the electrostatics of these devices at any other intermediate temperatures. In this work, we analyze the variation of band structure for Si, Ge and GaAs over different channel thicknesses at 0 K and 300 K (for which TB parameters are available), and show that the band curvature at the band minima has minor variation with temperature, whereas the change of band gap significantly affects the channel electrostatics. Based on this finding, we propose an approach to simulate the electrostatics of UTB devices, at any temperature between 0 K and 300 K, using TB parameters defined at 0 K, along with a suitable channel thickness and temperature dependent band gap correction.

In Ultra-thin Body (UTB) devices, besides the Ultra-thin (UT) nature of the channel, which manifests in terms of Quantum Confinement Effects (QCEs), the Band-offsets between the oxide and channel materials at their interface, also tends to strongly impact the channel electrostatics. Despite being very accurate in calculating the band-structure and hence considering QCEs for a given channel material, the Tight-Binding (TB) method tends to be more complicated to use at the channel/oxide interface of MOS devices, while on the other hand the Effective Mass Approximation (EMA) in spite of being less accurate, is a simpler approach to consider the effects of band-offsets at the interface. Given its accuracy, we firstly use the $sp^3d^5s^*$ TB method to calculate the Band-structure and then by considering significant k-points, efficiently incorporate the QCE into the electrostatics of Double-Gate (DG) Silicon-on-Insulator (SOI) MOS devices. Considering these results as a reference, with the assumption of an infinite potential well, we propose a modified Effective Mass Approximation (mEMA) approach, whereby introducing energy correction parameters, along with the effective mass parameters, all of which are shown to be gate bias, channel and oxide thickness dependent, the results obtained from the proposed approach are shown to have good agreement with the results from TB method. In order to analyze the effect of Conduction-Band Offset variations on the channel electrostatics parameters, we consider an $SiO_2$ layer of thickness of $1$ $nm$ and show the effect of different Band-offsets on the integrated charge density and gate capacitance, using the mEMA approach.

In this letter, through TCAD simulations, we show that the introduction of a thin paraelectric (PE) layer between the ferroelectric (FE) and dielectric (DE) layers in an MFIS structure, expands the design space for the FE layer enabling hysteresis-free and steep subthreshold behavior, even with a thicker FE layer. This can be explained by analyzing the FE-PE stack from a capacitance perspective where the thickness of the PE layer in the FE-PE stack has the effect of reducing the FE layer thickness, while also reducing the remnant polarization. Finally, for the same FE-PE-DE stack, analog performance parameters such as $\frac{g_{m}} g_{ds}}$ and $\frac{g_{m}}{I_{d}}$ are analyzed, showing good characteristics over a wide range of gate lengths, at low drain voltages, thus demonstrating applicability for low power applications.