This article reveals, analyzes and proposes the method to mitigate nonlinear effects of multi-sampled multi-update (MSMU) digital phase-shifted pulsewidth modulators (PS-DPWM) that appear in unbalanced multi-cell voltage-source converters (MC-VSCs). For balanced MC-VSCs, the harmonic cancellation of PS-DPWM allows for an increase in the sampling frequency, ensuring that the average current is acquired at the peaks, valleys, and intersections of all triangular carriers. For unbalanced operation, which is typically encountered in practice, e.g., due to cell voltage mismatch in multilevel MC-VSCs and inductance mismatch in interleaved MC-VSCs, harmonic cancellation of PS-DPWM is compromised and, thus, the increased sampling frequency brings switching ripple in the feedback signal. Since in MSMU control the modulating signal is also updated at peaks, valleys, and intersections of all carriers, this may cause vertical intersections between the modulating signal and the carriers, resulting in specific nonlinear effects. The nonlinearities are shown to introduce limit-cycle oscillations and output waveform distortion. A method to prevent such detrimental impact of MSMU-PS-PWM is also proposed. A simple analytical procedure is proposed to quantify the analyzed non-linear effects, revealing that they are more emphasized for higher levels of imbalance and control bandwidth. Moreover, the modulator nonlinearity is shown to decrease as the number of cells increases. The analyses are verified in simulations and experiments, using laboratory prototypes of three- and four-level MC-VSCs.

This article addresses switching noise propagation and its suppression in multi-rate control systems, where the inductor current is oversampled, digitally filtered and the control execution is decimated to single(double)-sampled pulse-width modulation (PWM). The operating points where the sampling instants occur near the switching ones are critical for switching noise sensitivity. It is shown that, when the number of the corrupted samples is high with respect to the number of samples used for filtering, typically considered moving average filters (MAFs) bring a detrimental impact. As an alternative, median filter (MED) is proposed. To decouple the ranking within MED from the switching ripple, repetitive ripple removal is added beforehand. Multi-rate PWM control with the proposed feedback filtering outperforms state-of-the-art double-sampled PWM by eliminating the well-known switching noise sensitivity for small and large duty cycles. In addition, noise-sensitive operating point regions that appear with MAF are successfully suppressed.

This paper addresses high frequency admittance modelling of current-controlled voltage source converters (VSCs). Recent studies have shown that harmonic instability may also occur at frequencies above the Nyquist frequency. To form an accurate multiple-frequency model in this frequency range, sidebands that originate from modulation and sampling must be examined. In this paper, an accurate small-signal model is developed taking into account an adequate digital pulse-width modulator (DPWM) representation, which allows to predict dependence of the frequency response on the steady-state DC (SSDC) operating point. It is shown that, when center-pulse sampling is implemented, PWM sidebands do not create additional loops leaving only sampling sidebands to be considered. Using the same approach as for SS-DC operation, a model which accurately represents admittance measurements during sinusoidal AC (S-AC) operation is developed. Its basis is a novel DPWM model suitable for S-AC regime, which allows to predict dependence of the VSC’s input admittance on the grid voltage magnitude. Experimental and simulated admittance measurements, performed on a single-phase two-level VSC during various SS-DC and S-AC regimes, show an excellent match with the proposed models up to twice the sampling frequency